Digital correlators are known to detect the presence of a predetermined sequence of digits, generally referred to as a correlation word, in a data stream. The correlation word is inserted into the data stream prior to transmission. Upon reception, the occurrence of the correlation word is detected by a correlation circuit and utilized to synchronize the operation of the receiving device. For example, in rotary head magnetic recorders it is known to record a known digital correlation word on tape at the beginning of each head path. At playback, presence of the correlation word is detected and utilized to synchronize the playback signal. In some applications it is desirable to detect two such synchronization signals, that is two different correlation words, for example one indicating the beginning of a scan or frame off tape, further referred to as a frame sync, and the other indicating the beginning of each data block within the frame, referred to as a block sync.
Generally, the known correlation word is stored in a memory, or on an electronic template. The incoming serial data stream is applied to a serial shift register, where it is shifted bit wise at the serial data rate. After each shift the data in the register is compared with the stored correlation word. Each matching bit produces a logic "true" output signal level, for example a logic one. The bits which do not match produce a "false" logic level, for example a logic zero. The number of matching bits is summed in a summing circuit, and the resulting sum is compared to a threshold. When the sum is below the threshold, it is assumed that the data in the shift register does not correspond to the correlation word. When the sum is equal to or exceeds the threshold, the correlation word is detected.
In high speed applications it is essential to maintain the speed of operation of the summing circuit at a maximum. Specifically, when using a synchronous digital summing circuit, the rate of clocking the data through that circuit must be equal to the input data rate, so that at each bit time a correlation result may be determined. High order binary summing circuits are known to operate at relatively slow speed, and when used in digital correlators, the operational speed of the entire correlation circuit is limited. Particularly, such summing circuits are not suitable in applications where it is necessary to detect relatively long correlation words in a high speed digital data stream. These circuits would generally slow down the correlation process, and thereby limit the application to slower data rates.
An example of a typical binary adder circuit having a parallel pipelined structure for handling summation and carry bits separately, is described in U.S. Pat. 4,660,165 to R. T. Masumoto. That type of circuit, referred to as pyramid carry adder, includes at each stage multiple bit adders. Each such multiple bit adder receives input addends of more then one binary order, in addition to a carry bit, and outputs a partial sum of the received addends The first stage produces as outputs multiple sum bits and a carry bit One or more additional stages separately combine partial sum outputs and carry outputs obtained from the previous stages, and produce separate carry and sum output bits in such a way that the number of carry bits is reduced As it is well known, the higher the order of an adder stage, the deeper the level of combinational logic utilized in the adder circuit, and therefore the longer the operational delay provided by that stage. While this known circuit operates entirely in the digital environment, its speed of operation, that is the rate of data to be processed, is limited by its slowest combinational logic path, which is the one having the highest level of combinational logic delay
As a further disadvantage, multibit adders are located further apart from each other and occupy a relatively large area on the silicon chip. Therefore, relatively long connecting lines are needed for sum and carry bits between the consecutive adder stages. With longer interconnect lines the routing delay time between each stage of the summing circuit increases, thereby also limiting the operating speed and obtainable bit rate for the overall data correlator circuit. In addition, the above mentioned pyramid type adders have a high density of logic elements at the input, with progressively decreasing density towards the output, thus creating a "funneling" effect in the distribution of logic circuit elements. In order to efficiently utilize the area of the silicon chip where the summing circuit is formed, the funneled circuit must be typically spread out over a square or rectangular area, whereby the routing distances between adjacent stages increase. Consequently, to increase the speed of operation it is desirable to provide a more even distribution of elements with minimized routing length between adder stages from the input to the output of the overall summing circuit.
Because of the relatively slow operational speed obtainable by known digital summing circuits, high speed data correlators have been known to utilize analog circuits for summing the number of bit matches resulting from the comparison with the correlation word. One such high speed correlator is described for example in U.S. Pat. No. 4,498,141, assigned to the assignee of this patent application. In that correlator for each bit match a known analog signal change is provided on a common terminal. Thus the high speed analog signal changes on the common terminal are proportional to the number of bit matches and they correspond to the summed analog signal. The changing analog signal on the common terminal is compared with an analog reference threshold signal to detect presence of the correlation word in the data stream. This particular correlator is capable of operating at a data rate over 100 MHz. This analog correlator however requires many discrete parts, is subject to noise pick-up, and has a less accurate threshold detection because of its sensitivity to component tolerances and temperature.